Cadence Unveils Industry’s First Fully Autonomous Virtual Engineer for Chip Design — Powered by NVIDIA

TLDR

• Announcement: Cadence ChipStack AI Super Agent extended to Level-5 autonomy
• Reveal: Computex 2026
• Key Tech: Built on NVIDIA Nemotron models, secured by NVIDIA OpenShell runtime
• Performance: 40X faster RTL validation cycles; 5-week verification loop reduced to less than a day
• Availability: Early-access customers in H2 2026

Cadence Pushes Chip Design Into the Autonomous Era

At Computex 2026, Cadence (Nasdaq: CDNS) announced the industry’s first fully autonomous virtual agentic AI design engineer, extending the ChipStack AI Super Agent to Level-5 autonomy. Built on Cadence’s AI-driven electronic design automation (EDA) portfolio with NVIDIA Nemotron models, and secured by the NVIDIA OpenShell runtime, the new agentic capabilities enable customers to run dynamic simulations in automated workflows — a step change for the global semiconductor industry.

The scale of the problem Cadence is solving is substantial. At NVIDIA, thousands of engineers are using billions of compute hours per year to run millions of tests to verify their designs. Each engineer will now use ChipStack agents to run hundreds of dynamic simulations with Cadence Xcelium Logic Simulation and Jasper Formal Verification, delivering over 40X faster RTL validation cycles and reducing a typical five-week verification loop to less than a day. That kind of cycle-time compression has direct implications for time-to-market on the most advanced silicon designs.

Paul Cunningham, senior vice president and general manager of the System Verification Group at Cadence, framed the strategic shift: “We see our customers using AI to let their expert engineers take on more ambitious silicon designs with greater speed and confidence. With the ChipStack AI Super Agent, we’re taking the next step — moving from AI that assists engineers to autonomous virtual engineers that can implement real design and verification work, grounded in our signoff-accurate engines and running in secure, governed environments so teams can innovate faster with confidence.”

From AI Assistance to Autonomous Engineering

The ChipStack AI Super Agent now operates at Level-5 autonomy, independently executing complex chip design and verification workflows while allowing engineers to inspect, guide, and collaborate as needed. Native integration with collaboration environments and compatibility with tools like Codex or Claude Code provides transparency into autonomous activity, helping teams stay connected to the system’s progress and decisions.

Rather than relying on step-by-step prompts, the ChipStack AI Super Agent evaluates intermediate results, determines next actions, and iterates toward closure across tasks such as specification understanding, RTL generation, verification planning, formal analysis, simulation, debug, and design convergence. This shifts engineers from executing individual tasks to supervising outcomes and guiding intent — a fundamental role change for the silicon design profession. Autonomous verification workflows shrink validation cycles that traditionally took weeks down to less than a day in leading-edge deployments.

Grounded in Engineering Truth, Secured for Production

A key Cadence differentiator is that autonomous agent behavior is tightly coupled with the company’s core physics-based design and verification engines. This keeps AI-directed actions grounded in proven computational models and signoff-accurate results, creating the trust needed for high-stakes engineering programs. For an industry where a single missed verification bug can cost millions in respin cycles, that grounding matters.

To support production deployment, the ChipStack AI Super Agent runs within the NVIDIA OpenShell runtime, a sandboxed environment for autonomous agents that enforces governance and helps protect sensitive IP through policy controls, isolation, and managed access to tools, infrastructure, and design data. Together, Cadence’s physics-based engines and OpenShell’s security architecture provide a practical path from supervised pilots to production-grade autonomous flows.

Timothy Costa, vice president and general manager of computational engineering at NVIDIA, added: “As semiconductor designs grow more complex, engineering teams need AI agents that can accelerate verification without compromising security, control, or trust. By securing Cadence’s ChipStack AI Super Agent with NVIDIA OpenShell and powering it with Nemotron models, Cadence is bringing governed autonomy to chip design workflows — giving customers a faster, more secure path to develop and validate advanced semiconductors.”

Cadence’s Rapid Agentic AI Cadence

This announcement reflects the speed of Cadence’s innovation in agentic AI, powered by NVIDIA. Following the acquisition of ChipStack in November 2025, Cadence launched its first product in February 2026 and expanded into a portfolio of AI super agents at CadenceLIVE in April, introducing ViraStack AI Super Agent for custom and analog design, InnoStack AI Super Agent for digital implementation and signoff, and Cadence AgentStack as the orchestration framework for coordinating agentic workflows across the design stack. Cadence is now extending those capabilities to full autonomy.

The pace is notable: from acquisition to Level-5 autonomous capability in roughly seven months, and from first product to a full super-agent portfolio in just a few months more. For chip designers evaluating EDA toolchains, that velocity signals Cadence’s intent to define the agentic AI category in semiconductor design rather than react to competitors.

Availability and Outlook

The Level-5 autonomous capabilities of the ChipStack AI Super Agent and the AgentStack orchestration framework are expected to be available to early-access customers in the second half of 2026. No general availability timeline has been disclosed yet.

Our Take

Cadence’s Level-5 autonomous chip design agent is a genuinely significant announcement, and the 40X RTL validation speedup is the kind of number that gets attention from semiconductor leadership. The technical foundation — physics-based engines from Cadence, Nemotron models and OpenShell runtime from NVIDIA — is the right architecture: trust comes from grounding AI in proven computational models, and security comes from a sandboxed runtime with policy controls. For chip designers dealing with exploding verification complexity at advanced nodes, this is the most credible path to autonomous silicon engineering we’ve seen.

The real question is production-readiness. “Level-5 autonomy” is a marketing term until customers have run real workloads through it, validated the signoff accuracy claims, and stress-tested the security architecture. Cadence’s H2 2026 early-access window will be the proving ground. If the results hold up — if autonomous ChipStack agents can match the verification quality of human-led flows on leading-edge designs — the role of verification engineers will fundamentally change, and the economics of advanced chip development will follow. Watch the early-access case studies when they land.